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INTEGRATED CIRCUITS
DATA SHEET
SAA8116 Digital PC-camera signal processor including microcontroller and USB interface
Product specification Supersedes data of 2000 Dec 6 File under Integrated Circuits, IC22 2001 May 04
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
FEATURES * Embedded microcontroller (80C51 core based) for control loops Auto Optical Black (AOB), Auto White Balance (AWB), Auto Exposure (AE) and USB interface control * Compliant for VGA CCD and VGA CMOS sensors (RGB Bayer) * USB 1.1 compliant bus-powered USB device with integrated power management and POR circuit * RGB processing * Optical black processing * Defect pixel concealment * Programmable colour matrix * RGB to YUV transform * Programmable gamma correction (including knee) * Programmable edge enhancement * Video formatter with SIF/QSIF downscaler * Compression engine * Flexible Measurement Engine (ME) with up to eight measurements per frame * Internal Pulse Pattern Generator (PPG) for wide range of VGA CCDs (Sony, Sharp and Panasonic) and frame rate selection * Programmable H and V timing for the support of CMOS sensors * Programmable output pulse for switched mode power supply of the sensor * 3-wire interface to control an external pre-processor IC, such as the TDA8787A: Correlated Double Sampling (CDS), Automatic Gain Control (AGC) and 10-bit ADC * Analog microphone/audio input to USB: Low DropOut (LDO) supply filter, microphone supply, low noise amplifier, programmable amplifier, PLL and ADC * Integrated analog USB driver (ATX) * Integrated main oscillator, including a clock PLL, which derives 48 MHz main system clock from a 12 or 48 MHz fundamental crystal. ORDERING INFORMATION TYPE NUMBER SAA8116HL PACKAGE NAME LQFP100 DESCRIPTION plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm GENERAL DESCRIPTION APPLICATION * USB PC-camera (video and audio).
SAA8116
The SAA8116 is a highly integrated third generation USB PC-camera ICs. It is the successor to the SAA8112HL and SAA8115HL. It processes the digitized sensor data and converts it to a high quality, compressed YUV signal. Together with the audio signal, this video signal is then properly formatted in USB packets. In addition, an 80C51 microcontroller derivative with five I/O ports, I2C-bus, 512 bytes of RAM and 32 kbytes of program memory is embedded in the SAA8116. The microcontroller is used in combination with the programmable statistical measurement capabilities to provide advanced AE, AWB and AOB. The microcontroller is also used to control the USB interface.
VERSION SOT407-1 SOT630-1
SAA8116ET TFBGA112 plastic thin fine-pitch ball grid array package; 112 balls; body 7 x 7 x 0.8 mm 2001 May 04 2
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SAA8116
QUICK REFERENCE DATA Measured over full voltage and temperature range: VDD = 3.3 V 10% and Tamb = 0 to 70 C; unless specified. SYMBOL VDD IDD(tot) Vi Vo f(i)xtal Ptot Tstg Tamb Tj Notes 1. Typical: VGA at 15 fps. 2. Maximum: SIF at 30 fps. 3. The crystal input frequency can be 12 or 48 MHz, depending on the use of the internal CPLL (selectable via pin XSEL). PARAMETER supply voltage total supply current input voltage output voltage crystal input frequency crystal frequency duty factor total power dissipation; note 1 VDD = 3.3 V; Tamb = 25 C (typ.) storage temperature ambient temperature junction temperature Tamb = 70 C VDD = 3.3 V; Tamb = 25 C (typ.) 3.0 V < VDD < 3.6 V 3.0 V < VDD < 3.6 V note 3 CONDITIONS - MIN. 3.0 TYP. 3.3 85(1) MAX. 3.6 105(2) V mA V V MHz % mW C C C UNIT
low voltage TTL compatible low voltage TTL compatible - - - -55 0 -40 12 or 48 - 50 280 - 25 - - 350 +150 70 +125
2001 May 04
3
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H 95 VSP WINDOW TIMING AND CONTROL REFERENCE TIMING PULSE PATTERN GENERATOR MODE DECODER V 96 ASCLK PCLK 10 9 PXL9 to PXL0 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 PREPROCESSING RGB RECONSTRUCTION STROBE SDATA SCLK 25 27 26 PRE-PROCESSING INTERFACE
BLOCK DIAGRAM
Philips Semiconductors
Digital PC-camera signal processor including microcontroller and USB interface
FV3, FV4 FV1, FV2 FH1, FH2
ROG CRST 97
RG
BCP, DCP
RESERVED2, RESERVED3
FS, FCDS 92 5, 6
SMP RESERVED1 23, 24 94 64 83, 84 ANALOG MODULES LDO SUPPLY FILTER MICROPHONE SUPPLY AUDIO LOW NOISE AMPLIFIER 57 58 59
1, 2 3, 98
91, 90 93
LDOIN LDOFIL LDOOUT
Y PROCESSING RGB PROCESSING RGB TO YUV UV PROCESSING
60
MICSUPPLY
4:2:2 FORMATTER
61 62
MICIN LNAOUT
MEASUREMENT ENGINE PROGRAMMABLE AUDIO GAIN AMPLIFIER 63 PGAININ
AUDIO PLL GPI1 GPI2 GPI3 LED FULLPOWER SNAPRES PRIVRES SDA, SCL EA ALE, PSEN 34 70 71 4 89 28 29 33, 32 54 49, 50 48, 51, 47, 52, 46, 53, 45 39, 38, 40, 37, 41, 35, 42, 36 VIDEO FORMATTER COMPRESSION ENGINE TRANSFER BUFFER 65, 66, 67 AUDIO DECIMATION AUDIO ADC Vref1, Vref2, Vref3 XSEL XIN XOUT ATXDP ATXDN DELAYATT PSEL PORE
4
VFC 80C51 MICROCONTROLLER USB INTERFACE AD14 to AD8
3
85 74 73 80 79 82 86
OSCILLATOR AND CPLL
ATX
SAA8116
2
72, 81 VDDA1, VDDA2
POWER MANAGEMENT
POR
69
3
75, 78, 68 AGND1 to AGND3
2
56, 21
6
7, 30, 43, 76, 87, 99 VDD1 to VDD6
8
8, 31, 44, 77, 88, 100, 55, 22 GND1 to GND8
P0.7 to P0.0
FCE673
Product specification
VDDD1, VDDD2
SAA8116
Fig.1 Block diagram (LQFP100).
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VSP WINDOW TIMING AND CONTROL REFERENCE TIMING PULSE PATTERN GENERATOR MODE DECODER PXL9 to PXL0 F2, F1, G3, G1, G2, H3, H1, H2, J3, J1 STROBE SDATA SCLK J4 K3 M2 GPI1 GPI2 GPI3 LED FULLPOWER SNAPRES PRIVRES SDA, SCL EA ALE, PSEN M5 D12 D11 C1 A6 M3 L3 K5, L4 K11 K10, M11 M10, M12, L10, J9, K9, L12, M9 M7, L7, K7, L6, L8, L5, M8, K6
Philips Semiconductors
Digital PC-camera signal processor including microcontroller and USB interface
FV3, FV4 H A4 V C4 ASCLK PCLK E3 E1 FV1, FV2 FH1, FH2 B5, C6
ROG CRST C5
RG
BCP, DCP
RESERVED2, RESERVED3
FS, FCDS A5 D2, D1 K2, L1
SMP RESERVED1 B4 G10 A8, B8 ANALOG MODULES LDO SUPPLY FILTER MICROPHONE SUPPLY AUDIO LOW NOISE AMPLIFIER J12 J10 H11 LDOIN LDOFIL LDOOUT
D4, C2, B1 A3
B3
Y PROCESSING PREPROCESSING RGB RECONSTRUCTION RGB PROCESSING RGB TO YUV UV PROCESSING
H12
MICSUPPLY
4:2:2 FORMATTER
H10 G11
MICIN LNAOUT
PRE-PROCESSING INTERFACE
MEASUREMENT ENGINE PROGRAMMABLE AUDIO GAIN AMPLIFIER G12 PGAININ
AUDIO PLL VIDEO FORMATTER COMPRESSION ENGINE TRANSFER BUFFER F12, F11, E12 AUDIO DECIMATION AUDIO ADC Vref1, Vref2, Vref3 XSEL XIN XOUT ATXDP ATXDN DELAYATT PSEL PORE
5
3
C7 B12 C11 A9 A10 C8 A7
VFC 80C51 MICROCONTROLLER USB INTERFACE
OSCILLATOR AND CPLL
ATX
AD14 to AD8
SAA8116
2
C12, B9 VDDA1, VDDA2
POWER MANAGEMENT
POR
D10
3
2
D9, C10, E11 J11, J2 VDDD1, VDDD2
6
D3, K4, K8, B11, B7, C3 VDD1 to VDD6
8
E2, M4, L9, A11, B6, A2, K12, K1
P0.7 to P0.0
MGU263
AGND1 to AGND3
GND1 to GND8
Product specification
SAA8116
Fig.2 Block diagram (TFBGA112).
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
PINNING SYMBOL FV1 FV2 FV3 LED FS FCDS VDD1 GND1 PCLK ASCLK PXL9 PXL8 PXL7 PXL6 PXL5 PXL4 PXL3 PXL2 PXL1 PXL0 VDDD2 GND8 BCP DCP STROBE SCLK SDATA SNAPRES PRIVRES VDD2 GND2 SCL SDA GPI1 P0.2 P0.0 PIN(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 BALL(2) TYPE(3) D4 B1 C2 C1 D2 D1 D3 E2 E1 E3 F2 F1 G3 G1 G2 H3 H1 H2 J3 J1 J2 K1 K2 L1 J4 M2 K3 M3 L3 K4 M4 L4 K5 M5 L5 K6 O O O O O O P P I O I I I I I I I I I I P P O O O O O I I P P I/O I/O I I/O I/O DESCRIPTION
SAA8116
vertical CCD transfer pulse output (or general purpose output) vertical CCD transfer pulse output (or general purpose output) vertical CCD transfer pulse output (or general purpose output) output to drive LED data sample-and-hold pulse output to TDA8787A (SHD) preset sample-and-hold pulse output to TDA8787A (SHP) supply voltage 1 for output buffers ground 1 for output buffers pixel input clock clock 1 (pixel clock) or clock 2 (2 x pixel clock) output for ADC or CMOS sensor pixel data input; bit 9 pixel data input; bit 8 pixel data input; bit 7 pixel data input; bit 6 pixel data input; bit 5 pixel data input; bit 4 pixel data input; bit 3 pixel data input; bit 2 pixel data input; bit 1 pixel data input; bit 0 supply voltage 2 for the digital core ground 8 for input buffers and predrivers optical black clamp pulse output to TDA8787A dummy clamp pulse output to TDA8787A strobe signal output to TDA8787A or general purpose output of the microcontroller serial clock output to TDA8787A or general purpose output of the microcontroller serial data output to TDA8787A or general purpose output of the microcontroller snapshot input or remote wake-up trigger input (programmable) privacy shutter input or remote wake-up trigger input (programmable) supply voltage 2 for input buffers and predrivers ground 2 for input buffers and predrivers I2C-bus clock input/output (master/slave) I2C-bus data input/output (master/slave) general purpose input 1 (Port 4; bit 6) microcontroller Port 0 bidirectional (data - address); bit 2 microcontroller Port 0 bidirectional (data - address); bit 0
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SYMBOL P0.4 P0.6 P0.7 P0.5 P0.3 P0.1 VDD3 GND3 AD8 AD10 AD12 AD14 ALE PSEN AD13 AD11 AD9 EA GND7 VDDD1 LDOIN LDOFIL LDOOUT MICSUPPLY MICIN LNAOUT PGAININ RESERVED1 Vref1 Vref2 Vref3 AGND3 PORE GPI2 GPI3 VDDA1 XOUT XIN AGND1 2001 May 04 PIN(1) 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 BALL(2) TYPE(3) L6 L7 M7 K7 L8 M8 K8 L9 M9 K9 L10 M10 K10 M11 M12 J9 L12 K11 K12 J11 J12 J10 H11 H12 H10 G11 G12 G10 F12 F11 E12 E11 D10 D12 D11 C12 C11 B12 D9 I/O I/O I/O I/O I/O I/O P P O O O O O O O O O I P P P - - O I O I O I I I P I I I P O I P DESCRIPTION
SAA8116
microcontroller Port 0 bidirectional (data - address); bit 4 microcontroller Port 0 bidirectional (data - address); bit 6 microcontroller Port 0 bidirectional (data - address); bit 7 microcontroller Port 0 bidirectional (data - address); bit 5 microcontroller Port 0 bidirectional (data - address); bit 3 microcontroller Port 0 bidirectional (data - address); bit 1 supply voltage 3 for output buffers ground 3 for output buffers microcontroller Port 2 output (address); bit 0 microcontroller Port 2 output (address); bit 2 microcontroller Port 2 output (address); bit 4 microcontroller Port 2 output (address); bit 6 address latch enable output for external latch program store enable output for external memory (active LOW) microcontroller Port 2 output (address); bit 5 microcontroller Port 2 output (address); bit 3 microcontroller Port 2 output (address); bit 1 external access select input; internal (HIGH) or external (LOW) program memory ground 7 for input buffers and predrivers supply voltage 1 for the digital core analog supply voltage for LDO supply filter external capacitor connection (filter of LDO) external capacitor connection (internal analog supply voltage for PLL; amplifier and ADC) microphone supply output microphone input low noise amplifier output programmable gain amplifier input test pin 1 (should be floating) reference voltage 1 (used in the amplifier and the ADC) reference voltage 2 (used in the ADC) reference voltage 3 (used in the ADC) analog ground 3 for PLL; amplifier and ADC external Power-on reset general purpose input 2 (Port 1; bit 4) general purpose input 3 (Port 3; bit 5) analog supply voltage for crystal oscillator (12 MHz, fundamental) oscillator output oscillator input analog ground 1 for crystal oscillator 7
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SYMBOL VDD4 GND4 AGND2 ATXDN ATXDP VDDA2 DELAYATT RESERVED2 RESERVED3 XSEL PSEL VDD5 GND5 FULLPOWER FH2 FH1 RG ROG SMP H V CRST FV4 VDD6 GND6 Notes 1. Pinning related to LQFP100 package. 2. Pinning related to TFBGA112 package. 3. I = input; O = output and P = power supply. PIN(1) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 BALL(2) TYPE(3) B11 A11 C10 A10 A9 B9 C8 A8 B8 C7 A7 B7 B6 A6 C6 B5 A5 C5 B4 A4 C4 B3 A3 C3 A2 P P P I/O I/O P O I I I I P P O O O O O O O I/O O O P P DESCRIPTION supply voltage 4 for input buffers and predrivers ground 4 for input buffers and predrivers analog ground 2 for ATX transceiver
SAA8116
negative driver of the differential data pair input/output (ATX) positive driver of the differential data pair input/output (ATX) analog supply voltage 2 for ATX transceiver delayed attach control output; connected with pull-up resistor on ATXDP (USB) test pin 2 (should be connected to GND) test pin 3 (should be connected to GND) crystal selection input POR selection input supply voltage 5 for output buffers ground 5 for output buffers full power signal output (active LOW) horizontal CCD transfer pulse output horizontal CCD transfer pulse output reset output for CCD output amplifier gate vertical CCD load pulse output switch mode pulse output for CCD supply horizontal synchronization pulse output vertical synchronization pulse input/output CCD charge reset output for shutter control vertical CCD transfer pulse output supply voltage 6 for output buffers ground 6 for output buffers
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SAA8116
89 FULLPOWER
84 RESERVED3
83 RESERVED2
82 DELAYATT
100 GND6
78 AGND2
79 ATXDN
81 VDDA2 80 ATXDP
88 GND5
77 GND4
97 CRST
99 VDD6
87 VDD5
handbook, full pagewidth
FV1 FV2 FV3 LED FS FCDS VDD1 GND1 PCLK
1 2 3 4 5 6 7 8 9
76 VDD4 75 AGND1 74 XIN 73 XOUT 72 VDDA1 71 GPI3 70 GPI2 69 PORE 68 AGND3 67 Vref3 66 Vref2 65 Vref1 64 RESERVED1 63 PGAININ 62 LNAOUT 61 MICIN 60 MICSUPPLY 59 LDOOUT 58 LDOFIL 57 LDOIN 56 VDDD1 55 GND7 54 EA 53 AD9 52 AD11 51 AD13 PSEN 50
FCE674
86 PSEL P0.5 40
ASCLK 10 PXL9 11 PXL8 12 PXL7 13 PXL6 14 PXL5 15 PXL4 16 PXL3 17 PXL2 18 PXL1 19 PXL0 20 VDDD2 21 GND8 22 BCP 23 DCP 24 STROBE 25 SCLK 26 SDATA 27 SNAPRES 28 PRIVRES 29 VDD2 30 GND2 31 SCL 32 SDA 33 GPI1 34 P0.2 35 P0.0 36 P0.4 37 P0.6 38 P0.7 39 P0.3 41 P0.1 42 VDD3 43 GND3 44 AD8 45 AD10 46 AD12 47 AD14 48 ALE 49
SAA8116
Fig.3 Pin configuration (LQFP100).
2001 May 04
9
85 XSEL
93 ROG
94 SMP
91 FH1
90 FH2
98 FV4
92 RG
95 H
96 V
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SAA8116
FCE778
handbook, halfpage
M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12
SAA8116ET
Fig.4 Ball configuration; bottom view of ball array (TFBGA112).
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Pinning for TFBGA112 BALL A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 n.c. GND6 FV4 H RG FULLPOWER PSEL RESERVED2 ATXDP ATXDN GND4 n.c. FV2 n.c. CRST SMP FH1 GND5 VDD5 RESERVED3 VDDA2 n.c. VDD4 XIN LED FV3 VDD6 V ROG FH2 XSEL DELAYATT n.c. AGND2 XOUT VDDA1 FCDS SYMBOL BALL D2 D3 D4 D9 D10 D11 D12 E1 E2 E3 E10 E11 E12 F1 F2 F3 F10 F11 F12 G1 G2 G3 G10 G11 G12 H1 H2 H3 H10 H11 H12 J1 J2 J3 J4 J9 J10 J11 FS VDD1 FV1 AGND1 PORE GPI3 GPI2 PCLK GND1 ASCLK n.c. AGND3 Vref3 PXL8 PXL9 n.c. n.c. Vref2 Vref1 PXL6 PXL5 PXL7 RESERVED1 LNAOUT PGAININ PXL3 PXL2 PXL4 MICIN LDOOUT MICSUPPLY PXL0 VDDD2 PXL1 STROBE AD11 LDOFIL VDDD1 SYMBOL BALL J12 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
SAA8116
SYMBOL LDOIN GND8 BCP SDATA VDD2 SDA P0.0 P0.5 VDD3 AD10 ALE EA GND7 DCP n.c. PRIVRES SCL P0.2 P0.4 P0.6 P0.3 GND3 AD12 n.c. AD9 n.c. SCLK SNAPRES GND2 GPI1 n.c. P0.7 P0.1 AD8 AD14 PSEN AD13
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
FUNCTIONAL DESCRIPTION The SAA8116 video processor has a very high level of programmability: 118 (8-bit) registers are dedicated for the Video Signal Processor (VSP), including Pulse Pattern Generator (PPG) and Measurement Engine (ME), plus 23 registers for the Video Formatter and Compressor (VFC). The SAA8116 can accept 8 to 10-bit digital data from various VGA sensors: CCD (progressive) or CMOS, with or without colour filters (see Table 1). Synchronization and video windows CCD SENSOR PULSE PATTERN GENERATOR The SAA8116 incorporates a PPG function, which can be used for VGA CCD sensors, see Table 1. Depending on the sensor type, an external inverter driver is required to convert the 3.3 V pulses to a voltage suitable for the CCD sensor used. The active video size is 640 x 480 for VGA. The total H x V size is 823 x 486 for VGA. A total of 19 internal registers make a high level of flexibility available for the PPG. FLEXIBLE HV TIMING The PPG module is not used with CMOS sensors. The SAA8116 provides some flexibility on the frame size to increase the range of applicable sensors (see Table 1). It is possible to program the position, width and polarity of the H and V signals. The output clock for the CMOS sensor is selectable between single and double pixel clock, including a programmable polarity.
SAA8116
The HV timing module can serve both as master or slave. When serving as a slave, the V pulse only is needed since the H pulse is internally derived from V by programming the number of pixels per line. VIDEO WINDOWS Several registers allow the definition of the optical black window, the active video input window, the active video output window and the measurement windows. Table 1 Typical SAA8116 compatible sensors BRAND Sony Sharp VGA CMOS Philips Hyundai Photobit PART NUMBER ICX098AK LZ24BP UPA1021 HV7131B PB-0320
SENSOR TYPE VGA CCD
Panasonic MN37771PT
Other sensors all sensors that fulfil the following criteria: * B and W; RGB Bayer colour filter * 8-bit, 9-bit or 10-bit output * CMOS or CCD sensors * progressive
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Video signal processor OPTICAL BLACK PROCESSING The first processing block of the SAA8116 is a digital clamp (denoted as PRE-PROCESSING in Fig.1). It is used to align the optical black level to zero or to any arbitrary value. The average value of the black is measured in the programmable optical black window and sent to the microcontroller for adjustment, if necessary. The value fixed by the microcontroller is subtracted from the incoming data stream. The optical black window has a fixed size of 16 pixels (horizontally) by 128 (vertically); the position of this window is fully programmable. Each of the four colour filter inputs has its own offset and gain. DEFECT PIXEL CONCEALMENT
SAA8116
Up to 128 Defect Pixel Coordinates (DPC) can be taken into account for concealment. The method is based either on a horizontal linear interpolation, or on a copy of a neighbouring pixel of the same colour. RGB COLOUR RECONSTRUCTOR In the RGB colour reconstructor (denoted as RGB RECONSTRUCTION in Fig.1), an RGB triplet is interpolated for every pixel on a 3 x 3 neighbourhood matrix. With B and W sensors, the RGB colour reconstructor can be disabled, thus maintaining the full sensor resolution. Vertical contours and video level information (white clip) are extracted at this stage (see Fig.5).
handbook, full pagewidth
LINE MEMORY RGB COLOUR SEPARATION
R G B
LINE MEMORY CCD inputs
White clip 10
FCE340
Edges
Fig.5 RGB reconstructor diagram.
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
COLOUR MATRIX
SAA8116
A programmable 3 x 3 colour matrix (see Fig.6) is used to convert the extracted colour information, R, G and B from the sensor colour space to a standard RGB colour space. With B and W sensors, a unity matrix is used. To control the white balance, the gain of the red and blue stream can be changed. Gamma and knee are combined in one function with adjustable gain.
handbook, full pagewidth
Rgain R or (2R-G)
x
R GAMMA/ KNEE
G or Y
COLOUR MATRIX Bgain
G
B or (2B-G)
x
FCE742
B
Fig.6 RGB processing diagram.
YUV PROCESSING Following the RGB processing, the R, G and B signals are converted to YUV 4 : 2 : 2 by a fixed matrix (see Fig.7). Then, the luminance and chrominance signals are processed separately. The luminance processing consists of edge enhancement. This feature is very flexible. First, it is possible to adjust the bandwidth and the level of the edge detection. Secondly, the amount of edge enhancement can be independently adjusted for the horizontal or vertical edge or for the high or low frequency edge.
The chrominance processing consists of a colour killer (white clip) and a UV gain control (see Fig.8). Processing is done on the multiplexed two-times-downsampled UV chrominance signals. The sensor input is used to kill the colour of over-exposed pixels. It is possible to adjust the number of pixels on which the correction is applied. The YUV processing block concludes with separate gain controls on the Y, U and V signals. These gains can be used to fine tune the Y, U and V colour balance and also to adjust the luminance and saturation without disturbing the AE and AWB control loops.
R CONVERSION MATRIX
Y
handbook, halfpage
G
B
DOWNSAMPLING AND MUX
FCE342
UV UV
WHITE CLIP
UV GAIN CONTROL
FCE743
UV
Fig.7 RGB to YUV conversion.
Fig.8 UV processing.
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
MEASUREMENT ENGINE The ME extracts statistical information from the video stream. These measurements are used for the auto-control loops in the microcontroller (AWB, AE and AGC). They can also be used for other purposes, such as colour detection. The measurements are performed on pre-formatted Y, U and V streams. It is possible to measure the accumulated value of the Y, U or V samples either in the full active video window or in a simple programmable window. Five parallel measurements of the luminance can be done for the auto exposure, each based on a proper window. Y, U and V can be measured independently for the auto white balance, all based on the same window. During each frame, the microcontroller has access to the measured values of the previous frame. Video formatter This block is used to convert the YUV 4 : 2 : 2 format to 4 : 2 : 0 required by the compression engine. The incoming 4 : 2 : 2 data is vertically filtered. In raw mode, this block is bypassed to create a full resolution snapshot. The formatter can also perform downscaling to SIF and QSIF (see Table 2). To avoid aliasing, this formatter also contains horizontal and vertical low pass pre-filters before downscaling. Table 2 Scaler modes OUTPUT FORMAT SIF 320 x 240
SAA8116
SENSOR TYPE VGA
SCALER MODES scaled half horizontally and vertically
QSIF 160 x 120 scaled quarter horizontally and vertically Compression engine The compression engine module (see Fig.9) can process VGA, SIF and QSIF, based on a Philips proprietary algorithm. The compression ratio is continuously programmable by setting a maximum bit cost limit. Input data can also be a raw RGB sensor data to perform optimum snapshot processing in the host software. The compression engine uses several strategies and Q-tables for optimum performance at a wide range of compression ratios (up to 8x). The required table must be selected via software. One table is optimized for compressing the raw VGA data. Real time decoding can be done in software on any PentiumTM or AMD-K6 platform.
handbook, full pagewidth
PREFILTER_SEL_UV PREFILTER_SEL_Y to transfer buffer
YUV7 to YUV0
PREFILTER
HORIZONTAL DOWNSCALING
DATA FORMATTER + VERTICAL DOWN SAMPLING
COMPRESSION ENGINE
VF_LIMITER SCALE_DATA
TABLE_SELECT LDC C_BITCOST_MSB C_BITCOST_LSB C_THRESHOLD_MSB C_THRESHOLD_LSB
FCE744
Fig.9 The video formatter and compression engine.
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 3 gives the available output formats and frame rates. Table 3 Video formats FRAME RATE 5 5 10 15 30 SIF 5 10 15 20 24 30 QSIF 5 10 15 20 24 30 raw; compressed compressed compressed compressed compressed compressed and uncompressed compressed compressed compressed compressed compressed compressed and uncompressed compressed and uncompressed compressed and uncompressed compressed and uncompressed compressed and uncompressed compressed and uncompressed COMPRESSION MODE
SAA8116
FORMAT VGA
The compressed data is streamed into a video FIFO, ready to be packed into USB formatted data blocks.
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Universal serial bus 1.1 core The USB core combines all functionalities for a USB 1.1 compliant full speed device. It formats the actual packets (video and audio) that are transferred to the USB and passes the incoming packets to the right end-point buffer. The end-point setup is composed of control, generic and isochronous types (see Table 4). All end-points can be enabled or disabled, except control end-points. All enabled end-points generate interrupts to the embedded microcontroller when they need to be serviced. The microcontroller can then use a set of commands via the internal parallel interface. Table 4
SAA8116
The video FIFO size allows demarcation of the video frames using one or more 0-length packets. The core also includes VID class support for the video end-point: headers and trailers enable data to be attached to the video frames that are passed over the USB. Eight 1-byte registers are dedicated for the headers, while four registers comprise the trailers. Each of the registers can be programmed by the microcontroller. An extra register, TR_HT_CONTROL, specifies how many bytes are inserted before or after the video data.
Mapping of logical to physical end-point numbers for the end-points PHYSICAL END-POINT 0 1 1 2 3 4 5 2 3 4 5 6 7 END-POINT TYPE control control generic generic generic generic isochronous isochronous DIRECTION out in out in in in in in BUFFER SIZE 16 16 8 8 8 8 92 programmable DOUBLE BUFFERED no no no no no no yes multi-buffered
LOGICAL END-POINT 0
ATX interface The SAA8116 contains an analog bus driver, called the ATX. This driver incorporates a differential amplifier and two single-ended buffers for the receiver part and two single-ended buffers for the transmitter part. The interface to the bus consists of a differential data pair (ATXDN and ATXDP). Microcontroller The embedded microcontroller is an 80C654 core (80C51 family). Ports P0 and P2 (plus ALE and PSEN) are available for connection to an emulator or to an external program EPROM (32 kbytes max.). The microcontroller can control the AOB, AE and AWB loops, and can download the settings for the internal registers from an optional EEPROM at power-up or reset.
A parallel interface is used to communicate with all internal modules, based on the MOVX@DPTR instruction. The microcontroller includes the following features: * 32 kbytes internal ROM * 512 bytes RAM * Hardware multi-master I2C-bus interface (the microcontroller can be used either as slave or master): P1.7 and P1.6 * Power-down mode * Two timers * P0 and P2 are pull-up ports * Three pins are available as general purpose inputs: GPI1 (P4.6), GPI2 (P1.4) and GPI3 (P3.5).
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 5 SFR NAME B ACC SIDAT SISTA PSW P4 IP P3 IE P2 SBUF SCON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPLl SP P0 Audio The SAA8116 contains a microphone supply, including a low-drop electronic supply filter, and an amplifier circuit composed of two stages: a Low Noise Amplifier (LNA) and a variable gain amplifier (VGA). The LNA has a fixed gain of 30 dB while the VGA can be programmed between 0 and 30 dB in steps of 2 dB. The frequency transfer characteristic of the audio path must be controlled via external high-pass or low-pass filters. 80C51 Special Function Registers (SFR) DESCRIPTION B register accumulator serial interface data serial interface status program status word Port 4 interrupt priority Port 3 interrupt enable Port 2 serial data buffer serial controller Port 1 timer high 1 timer high 0 timer low 1 timer low 0 timer mode timer control power control data pointer high data pointer low stack pointer Port 0 SFR ADDRESS F0H E0H DBH DAH D9H D8H D0H C0H B8H B0H A8H A0H 99H 98H 90H 8DH 8CH 8BH 8AH 89H 88H 87H 83H 82H 81H 80H DATA BIT 7 B7 ACC7 SA6 SD7 ST7 CR2 CY P4.7 - RD EA (AD15) - SM0 SDA - - - - GATE TF1 - - - SP7 P0.7 6 B6 ACC6 SA5 SD6 ST6 ENS1 AC P4.6 IP6 WR IE6 AD14 - SM1 SCL - - - - C/T TR1 - - - SP6 P0.6 5 B5 ACC5 SA4 SD5 ST5 STA F0 P4.5 IP5 T1 IE5 AD13 - SM2 P1.5 - - - - M1 TF0 - - - SP5 P0.5 4 B4 ACC4 SA3 SD4 ST4 STO RS1 P4.4 IP4 T0 IE4 AD12 - REN P1.4 - - - - M0 TR0 - - - SP4 P0.4 3 B3 ACC3 SA2 SD3 ST3 SI RS0 P4.3 PT1 INT1 ET1 AD11 - TB8 P1.3 - - - - GATE IE1 - - - SP3 P0.3 2 B2 ACC2 SA1 SD2 0 AA OV P4.2 PX1 INT0 EX1 AD10 - RB8 P1.2 - - - - C/T IT1 - - - SP2 P0.2
SAA8116
1 B1 ACC1 SA0 SD1 0 CR1 - P4.1 PT0 TXD ET0 AD9 - T1 P1.1 - - - - M1 IE0 PD - - SP1 P0.1
0 B0 ACC0 GC SD0 0 CR0 P P4.0 PX0 RXD EX0 AD8 - R1 P1.0 - - - - M0 IT0 IDL - - SP0 P0.0
SIADR serial interface address
SICON serial interface control
The PLL converts the 48 MHz to 256fs (fs = audio sample frequency). There are three modes for the PLL to achieve the sample frequencies of 48, 44.1 and 32 kHz or their derivatives (see Table 6). The bitstream ADC samples the mono audio signal. It runs at an oversample rate of 256 times the base sample rate. A decimator filter transforms the bitstream output to 16-bit samples. A digital mute option is available.
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 6 ADC clock frequencies and sample frequencies DIVIDING NUMBER 1 2 4 8 11.2896 1 2 4 8 12.2880 1 2 4 8 Note 1. Not supported. Power management USB requires the device to switch power states. The SAA8116 contains a power management module since the complete camera may not consume more than 500 A during the SUSPEND power state. This requires that even the crystal oscillator must be switched off. The SAA8116 is not functional except for some logic that enables the IC to wake up the camera. The SAA8116 incorporates remote wake-up (on two pins) to signal the host to resume operation when triggered. The power management module also sets a flag in register POWERMGT_STATUS. After a reset, the microcontroller should check this register and find the cause of the wake-up. Different causes may require different start-up routines. Miscellaneous functions Some additional functions are integrated in the SAA8116 to provide a cost effective application. SERIAL INTERFACE WITH THE PRE-PROCESSOR With CCD image sensors, the pre-processor (e.g. TDA8787A) is controlled over a 3-wire serial interface. It is adapted to shift out 16 bit settings. For flexibility, the output pins can also be programmed as three general output pins using register PIN_CONFIG_1. SAMPLE ADC CLOCK FREQUENCY (MHz) (kHz) 32 16 8 note 1 44.1 22.05 11.025 5.5125 48 24 12 6 4.096 2.048 1.042 note 1 5.6448 2.8224 1.4112 0.7056 6.144 3.072 1.536 0.768 CLOCK PLL
SAA8116
CLOCK (MHz) 8.1920
The SAA8116 runs on an internal master clock of 48 MHz, which can be derived from either a 48 or 12 MHz fundamental crystal. When it is derived from a 12 MHz fundamental crystal, an internal clock PLL transfers the 12 MHz to 48 MHz, with a 50% duty cycle. A 48 MHz third overtone crystal can also be used but requires an external LC circuit. RING OSCILLATOR To generate several time constants for power state switching, a digital counter running on an integrated ring oscillator is incorporated, thus saving pins and commonly used external RC components. POWER-ON RESET (POR) A POR function is integrated to generate a reset during the start-up of the power supply and during a power fail. It includes a fixed threshold detector (2.6 V) and a reset generator. The reset output has a built-in delay with a duration determined by the ring oscillator (around 100 ms). An external POR can be used. MODE CONTROL Two pins are dedicated to control the operational modes of the SAA8116 (see Table 7). Table 7 XS 0 0 1 1 Mode control PS 0 1 0 1 MODE application mode (48 MHz crystal; internal POR) application mode (48 MHz crystal; external POR) application mode (12 MHz crystal; internal POR) application mode (12 MHz crystal; external POR)
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
CONTROL REGISTER DESCRIPTION This specification gives an overview of all internal registers. Several modules (VSP, VFC, PPG, USB, audio and power management) communicate with the internal microcontroller via a common parallel interface. The protocol is based on a standard MOVX@DPTR instruction. A relative address (DPH) is used to select one Table 8 Register list NAME FUNCTION FORMAT
SAA8116
of the modules (via Port 2), while register addresses and data are exchanged via Port 0. VSP, VFC and PPG registers A first MOVX@DPTR instruction enables to select the module (via DPH) and the register address. A second one communicates the data (read or write).
ADDRESS Write registers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x00H 0x01H 0x02H 0x03H 0x04H 0x05H 0x06H 0x07H 0x08H 0x09H
RANGE
VSP_CONTROL0 VSP_CONTROL1 OB_K1 OB_K2 OB_K3 OB_K4 PRE_MAT_K1 PRE_MAT_K2 PRE_MAT_K3 PRE_MAT_K4
control register for VSP data path control register for VSP data path fixed optical black level for K1 pixel fixed optical black level for K2 pixel fixed optical black level for K3 pixel fixed optical black level for K4 pixel pre-gain for K1 pixel pre-gain for K2 pixel pre-gain for K3 pixel pre-gain for K4 pixel threshold for white clip detector colour matrix coefficient p11 colour matrix coefficient p12 colour matrix coefficient p13 colour matrix coefficient p21 colour matrix coefficient p22 colour matrix coefficient p23 colour matrix coefficient p31 colour matrix coefficient p32 colour matrix coefficient p33 red gain for white balance correction blue gain for white balance correction control of gamma/knee level vertical contour control contour level dependency level
see Table 9 byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte
n.a. [-128 to 127] [-128 to 127] [-128 to 127] [-128 to 127]
see Table 10 n.a.
0x0AH WHITE_CLIP_THR 0x0BH reserved 0x0CH COL_MAT_P11 0x0DH COL_MAT_P12 0x0EH COL_MAT_P13 0x0FH 0x10H 0x11H 0x12H 0x13H 0x14H 0x15H 0x16H 0x17H 0x18H 0x19H COL_MAT_P21 COL_MAT_P22 COL_MAT_P23 COL_MAT_P31 COL_MAT_P32 COL_MAT_P33 COL_MAT_RGAIN COL_MAT_BGAIN GAMMA_KNEE VC_CNTRL CLDLEV
768 + [0 to 255] [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [0 to 255]/128 [0 to 255]/64
see Table 11 n.a. see Table 12 n.a. byte [0 to 255]/2
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
ADDRESS 26 NAME FUNCTION horizontal contour BPF low gain (MS)/horizontal contour BP high gain (LS) contour noise coring level contour gain factor Y gain factor (luminance) U (B - Y) gain factor V (R - Y) gain factor AWB_A (ME) AWB_B (ME) AWB_C (ME) AWB_D (ME) AWB_E (ME) AWB_F (ME) display measurement window select display level in use with several display functions setup in digital output control data (LS byte) for analog processing control data (MS byte) for analog processing preset value of pixel counter (by default = 0) FORMAT nibble
SAA8116
RANGE [0 to 15]/16
0x1AH HCLGAIN/HCHGAIN
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
0x1BH CNCLEV 0x1CH CONGAIN 0x1DH YGAIN 0x1EH UGAIN 0x1FH 0x20H 0x21H 0x22H 0x23H 0x24H 0x25H 0x26H 0x27H 0x28H 0x29H VGAIN AWB_A AWB_B AWB_C AWB_D AWB_E AWB_F reserved DMWSEL DISPLEV DIG_SETUP
6 bits 6 bits byte byte byte byte byte byte byte byte byte
[0 to 63]/2 [0 to 63]/16 [0 to 255]/128 [0 to 255]/128 [0 to 255]/128 [-128 to 127]/128 [-128 to 127]/128 [-128 to 127]/128 [-128 to 127]/128 [0 to 255] [0 to 255]
see Table 13 n.a. see Table 14 n.a. byte byte byte byte [0 to 255] [0 to 255] [0 to 255] [0 to 255]
0x2AH PRE_SI_LSB 0x2BH PRE_SI_MSB 0x2CH PIXCNT_PRESET_LSB 0x2DH NLINE_PRESET_MSB 0x2EH LINECNT_PRESET_LSB
number of lines per frame + MSBs see Table 15 n.a. of preset register (by default = 6) preset value for line counter; line number 0 is undefined (by default = 1) number of pixels per line (by default = 55) number of line for double buffer update control registers first line optical black window first pixel optical black window starting position of the active window defining the ME windows (by default = 15) position of positive edge of HREF on a line (by default = 3) byte [1 to 255]
47 48 49 50 51
0x2FH 0x30H 0x31H 0x32H 0x33H
NPIX CTR_UPD_LINE OB_STARTLINE OB_STARTPIXEL PIX_START_ACTWIN_ME
byte byte byte byte 4 bits
768 + [0 to 255] 1 + 2 x [0 to 255] 2 x [0 to 255] 4 x [0 to 255] [0 to 15]
52 53
0x34H 0x35H
HREFSTART HOUT_PE_LSB
4 bits
2 x [0 to 15] [0 to 255]
position of positive edge of HOUT byte
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
ADDRESS 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 0x36H 0x37H 0x38H 0x39H NAME HOUT_NE_LSB VOUT_HPE_LSB VOUT_VPE_LSB VOUT_HNE_LSB FUNCTION position of negative edge of HOUT horizontal position of positive edge of VOUT vertical position of positive edge of VOUT horizontal position of negative edge of VOUT vertical position of negative edge of VOUT MSB of VHOUT position definitions (part 1) MSB of VHOUT position definitions (part 2) vertical position of positive edge of HOUT window vertical position of negative edge of HOUT window selects the number of extended active pixels (by default = 0) AWB_window (Vstart; Hstart) AWB_window (Vstop; Hstop) AE_window no. 0 (Vstart; Hstart) AE_window no. 0 (Vstop; Hstop) AE_window no. 1 (Vstart; Hstart) AE_window no. 1 (Vstop; Hstop) AE_window no. 2 (Vstart; Hstart) AE_window no. 2 (Vstop; Hstop) AE_window no. 3 (Vstart; Hstart) AE_window no. 3 (Vstop; Hstop) AE_window no. 4 (Vstart; Hstart) AE_window no. 4 (Vstop; Hstop) RAM write pointer for DPC RAM RAM write data DPC RAM FORMAT byte byte byte byte byte
SAA8116
RANGE [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255]
0x3AH VOUT_VNE_LSB 0x3BH VHOUT_MSB_1 0x3CH VHOUT_MSB_2 0x3DH HOUTWIN_VPE_LSB 0x3EH HOUTWIN_VNE_LSB 0x3FH 0x40H 0x41H 0x42H 0x43H 0x44H 0x45H 0x46H 0x47H 0x48H 0x49H XSEL ME_WIN_START_AWB ME_WIN_STOP_AWB ME_WIN_START_AE_0 ME_WIN_STOP_AE_0 ME_WIN_START_AE_1 ME_WIN_STOP_AE_1 ME_WIN_START_AE_2 ME_WIN_STOP_AE_2 ME_WIN_START_AE_3 ME_WIN_STOP_AE_3
see Table 16 n.a. see Table 17 n.a. byte byte [0 to 255] [0 to 255]
see Table 18 n.a. byte byte byte byte byte byte byte byte byte byte byte byte byte byte 3 x [0 to 127] [0 to 255]
0x4AH ME_WIN_START_AE_4 0x4BH ME_WIN_STOP_AE_4 0x4CH DPCRAMPTR 0x4DH DPCRAMDATA 0x4EH reserved 0x4FH 0x50H 0x51H 0x52H 0x53H 0x54H 0x55H 0x56H reserved TR_HEADER #0 TR_HEADER #1 TR_HEADER #2 TR_HEADER #3 TR_HEADER #4 TR_HEADER #5 TR_HEADER #6
data for header byte no. 0 data for header byte no. 1 data for header byte no. 2 data for header byte no. 3 data for header byte no. 4 data for header byte no. 5 data for header byte no. 6 22
byte byte byte byte byte byte byte
2001 May 04
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
ADDRESS 87 88 89 90 91 92 93 94 95 96 97 98 99 0x57H 0x58H 0x59H NAME TR_HEADER #7 TR_TRAILER #0 TR_TRAILER #1 FUNCTION data for header byte no. 7 data for trailer byte no. 0 data for trailer byte no. 1 data for trailer byte no. 2 data for trailer byte no. 3 header trailer control SMP period in units 4 x clk48_period SMP low time in units 4 x clk48_period PPG control register 0 (by default = 0) PPG control register 1 (by default = 64) controls mode of FH1; FH2 and RG (by default = 0) controls inversion of vertical FV1; FV2; FV3; FV4 and ROG signals (by default = 0) controls inversion of horizontal signals (by default = 0) controls inversion of misc. signals and sets additional mode controls (by default = 0) FORMAT byte byte byte byte byte
SAA8116
RANGE
0x5AH TR_TRAILER #2 0x5BH TR_TRAILER #3 0x5CH TR_HT_CONTROL 0x5DH SMP_PERIOD 0x5EH SMP_LOWTIME 0x5FH 0x60H 0x61H 0x62H 0x63H reserved PPG_CONTROL_0 PPG_CONTROL_1 PPG_H_CTRL PPG_V_INV
see Table 19 n.a. byte byte 1 + [0 to 255] 1 + [0 to 255]
see Table 20 n.a. see Table 21 n.a. see Table 22 n.a. see Table 23 n.a.
100 0x64H 101 0x65H
PPG_H_INV PPG_MISC_INV
see Table 24 n.a. see Table 25 n.a.
102 0x66H 103 0x67H 104 0x68H
PPG_SHUTTERSPEED_V_LSB shutter speed line number (by default = 0) PPG_SHUTTERSPEED_H_LSB shutter speed CRST start (by default = 0) PPG_SHUTTERSPEED_MSB MSB for shutter speed control (line number; CRST start) (by default = 0) starting position control for BCP pulse (by default = 0) stopping position control for BCP pulse (by default = 0) starting position control for DCP pulse (by default = 0) stopping position control for DCP pulse (by default = 0) MSB for start/stopping position control for BCP/DCP pulses (by default = 0) starting position control for ROG1 pulse (by default = 0) 23
see Table 26 see Table 27 see Table 28 n.a.
105 0x69H
PPG_BCP_START_LSB
see Table 29 see Table 30 see Table 31 see Table 32 see Table 33
106 0x6AH PPG_BCP_STOP_LSB 107 0x6BH PPG_DCP_START_LSB 108 0x6CH PPG_DCP_STOP_LSB 109 0x6DH PPG_BCP_DCP_MSB
110 0x6EH PPG_ROG1_START_LSB
see Table 34
2001 May 04
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
ADDRESS 111 0x6FH 112 0x70H 113 0x71H 114 0x72H NAME PPG_ROG1_STOP_LSB PPG_ROG2_START_LSB PPG_ROG2_STOP_LSB PPG_ROG1_2_MSB FUNCTION stopping position control for ROG1 pulse (by default = 0) starting position control for ROG2 pulse (by default = 0) stopping position control for ROG2 pulse (by default = 0) MSB for start/stopping position control for ROG1/2 pulses (by default = 0) FORMAT see Table 35 see Table 36 see Table 37 see Table 38
SAA8116
RANGE
115 0x73H
VFC_CONTROL_0
control register for video formatter see Table 39 n.a. and compression module (by default = 1) control register for video formatter see Table 40 n.a. and compression module (by default = 0) sets value for limiter output of video formatter (by default = 0) bit cost for compression module (MSB) (by default = 0) bit cost for compression module (LSB) (by default = 0) fixed length coding threshold for compression module (MSB) (by default = 0) fixed length coding threshold for compression module (LSB) (by default = 0) byte byte byte byte [0 to 255] 28 x [0 to 255] [0 to 255] 28 x [0 to 255]
116 0x74H
VFC_CONTROL_1
117 0x75H 118 0x76H 119 0x77H 120 0x78H
VF_LIMITER C_bitcost_MSB C_bitcost_LSB C_THRESHOLD_MSB
121 0x79H
C_THRESHOLD_LSB
byte
[0 to 255]
122 0x7AH TR_CONTROL 123 0x7BH VFC_VS_V_SHFT 124 0x7CH reserved 125 0x7DH reserved 126 0x7EH PIN_CONFIG_0 127 0x7FH PIN_CONFIG_1 Read registers 192 0xC0H ME_AWB_Y_MSB 193 0xC1H ME_AWB_U_MSB 194 0xC2H ME_AWB_V_MSB 195 0xC3H ME_AE_#0_MSB 196 0xC4H ME_AE_#1_MSB 197 0xC5H ME_AE_#2_MSB 198 0xC6H ME_AE_#3_MSB 199 0xC7H ME_AE_#4_MSB 2001 May 04
control register for transfer module bit (video processing) (by default = 0) V_shift of internal line counter 3 bits w.r.t. the VS pulse (by default = 0)
n.a. [0 to 7]
control pin configuration control pin configuration
see Table 41 n.a. see Table 42 n.a.
MSB part of ME_AWB_Y MSB part of ME_AWB_U MSB part of ME_AWB_V MSB part of ME_AE_no. 0 MSB part of ME_AE_no. 1 MSB part of ME_AE_no. 2 MSB part of ME_AE_no. 3 MSB part of ME_AE_no. 4 24
byte byte byte byte byte byte byte byte
[0 to 31] [0 to 31] [0 to 31] [0 to 31] [0 to 31] [0 to 31] [0 to 31] [0 to 31]
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
ADDRESS NAME FUNCTION ISB part of ME_AWB_Y ISB part of ME_AWB_U ISB part of ME_AWB_V ISB part of ME_AE_no. 0 ISB part of ME_AE_no. 1 ISB part of ME_AE_no. 2 ISB part of ME_AE_no. 3 ISB part of ME_AE_no. 4 LSB part of ME_AWB_Y LSB part of ME_AWB_U LSB part of ME_AWB_V LSB part of ME_AE_no. 0 LSB part of ME_AE_no. 1 LSB part of ME_AE_no. 2 LSB part of ME_AE_no. 3 LSB part of ME_AE_no. 4 measured optical black level read back of double-buffered RGAIN read back of double-buffered BGAIN FORMAT byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte
SAA8116
RANGE [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255]
200 0xC8H ME_AWB_Y_ISB 201 0xC9H ME_AWB_U_ISB 202 0xCAH ME_AWB_V_ISB 203 0xCBH ME_AE_#0_ISB 204 0xCCH ME_AE_#1_ISB 205 0xCDH ME_AE_#2_ISB 206 0xCEH ME_AE_#3_ISB 207 0xCFH ME_AE_#4_ISB 208 0xD0H ME_AWB_Y_LSB 209 0xD1H ME_AWB_U_LSB 210 0xD2H ME_AWB_V_LSB 211 0xD3H ME_AE_#0_LSB 212 0xD4H ME_AE_#1_LSB 213 0xD5H ME_AE_#2_LSB 214 0xD6H ME_AE_#3_LSB 215 0xD7H ME_AE_#4_LSB 216 0xD8H ME_OB_LEVEL 217 0xD9H READBACK_RGAIN 218 0xDAH READBACK_BGAIN
Table 9
Register CONTROL 0 (address: 0x00H) BIT PARAMETER
7 0 1
6
5
4
3
2
1
0 EN_CLK_DPC_RAM: control defect pixel concealment RAM clock disabled enabled EN_DPC: control defect pixel concealment
0 1 0 1 X X X 0 1 X 2001 May 04
disabled enabled CLK_IF_RESET: control clk1/clk2 interface free running (by default) reset toggle phase for line in colour separation toggle phase for pixel in colour separation reserved FORCE_AWBVAL: control AWB window enabled disabled (integral AWB measurement) reserved 25
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 10 Register CONTROL 1 (address: 0x01H) BIT PARAMETER 7 0 0 1 1 6 0 1 0 1 0 1 X X 0 1 0 0 X 0 1 X 5 4 3 2 1 0 DISP_CNTRL: select display signal no display D_WC (white clipped pixels) D_AWBVAL (pixels according to AWBVAL) D_MWG (measurement windows) RGB_SEP_OFF: RGB reconstructor for raw data mode enabled (normal RGB mode) disabled (raw data mode) reserved VCF_GAIN: vertical contour filter gain double normal WH_CL_MAP: white clip mapping on UV-grid [0 0 1 0 0] spreading filter [0 1 1 1 0] spreading filter [1 1 1 1 1] spreading filter
SAA8116
Table 11 Register GAMMA_KNEE (address: 0x17H) BIT PARAMETER 7 0 1 0 1 X X X X X X 6 5 4 3 2 1 0 control scaler (5/8 gain) disabled (transparent mode) enabled (normal operation) control knee disabled enabled gamma balance [0 to 63]/64
Table 12 Register VC_CNTRL (address: 0x18H) BIT PARAMETER 7 0 1 X X X X X X X 6 5 4 3 2 1 0 control vertical contour horizontal low pass filter disabled enabled vertical contour COMB filter gain [0 to 7]/8 vertical contour gain [0 to 15]/16
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 13 Register DMWSEL (address: 0x27H) BIT PARAMETER 7 X 0 1 0 1 0 1 X 0 1 0 1 0 1 6 5 4 3 2 1 0 undefined display measurement window #A for line #3 disabled enabled display measurement window #B for line #2 disabled enabled display measurement window #A for line #2 disabled enabled undefined display measurement window #A for line #1 disabled enabled display measurement window #B for line #0 disabled enabled display measurement window #A for line #0 disabled enabled
SAA8116
Table 14 Register DISPLEV (address: 0x28H) BIT PARAMETER 7 X X 6 X X 5 X X 4 X X X X X X 3 X 2 X 1 X 0 X set defect pixel display level in defect pixel display mode [4 x [0 to 255]] set Y (luminance) display level to other display modes [16 x [0 to 15]] set U display level to other display modes [64 x [-2 to 1]] set V display level to other display modes [64 x [-2 to 1]]
Table 15 Register NLINE_PRESET_MSB (address: 0x2DH) BIT PARAMETER 7 X 6 X X X Note 1. Internal LINECNT range is [1 to 511]; no line zero. X X X X 5 4 3 2 1 0 bits 8 and 9 for PIXCNT_PRESET (by default = 0) bit 8 for LINECNT_PRESET (by default = 0; note 1) number of lines in a frame [480 + [0 to 31]] (by default = 6)
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 16 Register VHOUT_MSB_1 (address: 0x3BH) BIT PARAMETER 7 X 6 X X X X X X Note 1. Internal LINECNT range is [1 to 511]; no line zero. Table 17 Register VHOUT_MSB_2 (address: 0x3CH) BIT PARAMETER 7 X 6 X 5 X X X X X X Note 1. Internal LINECNT range is [1 to 511]; no line zero. Table 18 Register XSEL (address: 0x3FH) BIT PARAMETER 7 X 6 X 5 X X X X X X 4 3 2 1 0 reserved mode control for pixel extender 4 3 2 1 0 reserved select HOUT polarity bit 8 for HOUTWIN_VNE; note 1 bit 8 for HOUTWIN_VPE; note 1 bit 8 for VOUT_VNE; note 1 bit 8 for VOUT_VPE; note 1 X 5 4 3 2 1 0 bits 8 and 9 for VOUT_HNE; note 1 bits 8 and 9 for VOUT_HPE; note 1 bits 8 and 9 for HOUT_NE bits 8 and 9 for HOUT_PE
SAA8116
Table 19 Register TR_HT_CONTROL (address: 0x5CH BIT PARAMETER 7 X 0 1 X X X 0 1 X 2001 May 04 X 6 5 4 3 2 1 0 undefined HEAD_ENA: control header transfer disabled enabled HEAD_LEN: header length TRAIL_ENA: control trailer transfer disabled enabled TRAIL_LEN: trailer length 28
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 20 Register PPG_CONTROL_0 (address: 0x60H) BIT PARAMETER 7 X 6 X 5 X 0 1 0 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 X 4 3 2 1 0 undefined SHUTTER_UPDATE_BUFFER: control shutter speed immediate (by default) buffered during vertical blanking select PPG power mode operational (by default) resume select PPG timing mode (VGA sensor) frame rate = 30 fps (LLC = 24.0 MHz) frame rate = 24 fps (LLC = 19.2 MHz) frame rate = 20 fps (LLC = 16.0 MHz) frame rate = 15 fps (LLC = 12.0 MHz) frame rate = 10 fps (LLC = 8.0 MHz) frame rate = 5 fps (LLC = 4.0 MHz) undefined
SAA8116
2001 May 04
29
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 21 Register PPG_CONTROL_1 (address: 0x61H) BIT PARAMETER 7 X 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 X 0 1 1 X 0 1 6 5 4 3 2 1 0 reserved select frequency for compression clock CLK_C off 2.0 MHz 2.4 MHz 4.0 MHz 4.8 MHz 6.0 MHz 8.0 MHz 9.6 MHz 12 MHz (by default) 16 MHz 19.2 MHz 24 MHz reserved select VGA sensor type reserved VGA type 1 (Sharp LZ24BP; Sony ICX098AK) VGA type 2 (Panasonic MN37771PT) X reserved
SAA8116
2001 May 04
30
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 22 Register PPG_H_CTRL (address: 0x62H) BIT PARAMETER 7 X 0 1 0 0 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 0 0 0 1 1 Note 1. If bits [5 to 3] equal bits [2 to 0] then FH2 is the inverse of FH1. 0 0 1 1 X X 0 1 0 1 0 1 6 5 4 3 2 1 0 reserved set RG pulse width nominal value RG_SHORT: half of nominal value FH2_CTRL; note 1 blanked to HIGH; starts LOW blanked to LOW; starts HIGH blanked to LOW; starts LOW blanked to HIGH; starts HIGH no horizontal blanking; pulse inverted no horizontal blanking FH1_CTRL; note 1 blanked to LOW; starts HIGH blanked to HIGH; starts LOW blanked to HIGH; starts HIGH blanked to LOW; starts LOW no horizontal blanking; pulse inverted no horizontal blanking
SAA8116
2001 May 04
31
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 23 Register PPG_V_INV (address: 0x63H) BIT PARAMETER 7 6 0 1 0 1 0 1 0 1 0 1 0 1 X Note X 5 4 3 2 1 0 FV4_INV negative pulses positive pulses FV3_INV negative pulses positive pulses FV2_INV positive pulses negative pulses FV1_INV positive pulses negative pulses ROG1_INV; note 1 negative pulses positive pulses ROG2_INV; note 1 negative pulses positive pulses reserved
SAA8116
1. ROG1_INV and ROG2_INV are related to ROG_SEL (see Table 41; PIN_CONFIG_0[0]). If ROG_SEL = 0, then ROG2_INV is activated (with Sony or Sharp CCD applications) and ROG1_INV is disabled. If ROG_SEL = 1, then ROG1_INV is activated (with Panasonic CCD applications) and ROG2_INV is disabled.
2001 May 04
32
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 24 Register PPG_H_INV (address: 0x64H) BIT PARAMETER 7 0 1 0 1 0 1 0 1 0 1 X 0 1 0 1 6 5 4 3 2 1 0 CLK2_INV nominal pulses inverted pulses CLK1_INV nominal pulses inverted pulses FS_INV negative pulses positive pulses FCDS_INV negative pulses positive pulses RG_INV negative pulses positive pulses reserved FH2_INV positive pulses negative pulses FH1_INV positive pulses negative pulses
SAA8116
2001 May 04
33
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 25 Register PPG_MISC_INV (address: 0x65H) BIT PARAMETER 7 X 0 1 X 0 1 0 1 0 1 0 1 0 1 6 5 4 3 2 1 0 reserved SELECT_FV3 FV3 equals FV2 FV3 equals FV4 (with VGA type 1 sensors) reserved CRST_INV negative pulses positive pulses BCP_INV positive pulses negative pulses DCP_INV positive pulses negative pulses H_INV positive pulses negative pulses V_INV positive pulses negative pulses
SAA8116
Table 26 Register PPG_SHUTTERSPEED_V_LSB (address: 0x66H) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of line number (9 bits) on which shutter speed is updated
Table 27 Register PPG_SHUTTERSPEED_H_LSB (address: 0x67H) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) on which shutter speed is updated
2001 May 04
34
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 28 Register PPG_SHUTTERSPEED_MSB (address: 0x68H) BIT PARAMETER 7 X 6 X 5 X 4 X 0 1 X X 3 2 1 0 reserved SENSOR_TYPE Sharp Sony 2 MSBs of pixel number (10 bits) X MSB of line number (9 bits) Table 29 Register PPG_BCP_START_LSB (address: 0x69H) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) where BCP starts
SAA8116
Table 30 Register PPG_BCP_STOP_LSB (address: 0x6AH) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) where BCP stops
Table 31 Register PPG_DCP_START_LSB (address: 0x6BH) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) where DCP starts
Table 32 Register PPG_DCP_STOP_LSB (address: 0x6CH) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) where DCP stops
Table 33 Register PPG_BCP_DCP_MSB (address: 0x6DH) BIT PARAMETER 7 X 6 X X X X X X 5 4 3 2 1 0 2 MSBs of PPG_DCP_STOP 2 MSBs of PPG_DCP_START 2 MSBs of PPG_BCP_STOP X 2 MSBs of PPG_BCP_START
2001 May 04
35
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 34 Register PPG_ROG1_START_LSB (address: 0x6EH) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) where ROG1 starts
SAA8116
Table 35 Register PPG_ROG1_STOP_LSB (address: 0x6FH) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) where ROG1 stops
Table 36 Register PPG_ROG2_START_LSB (address: 0x70H) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) where ROG2 starts
Table 37 Register PPG_ROG2_STOP_LSB (address: 0x71H) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 8 LSBs of pixel number (10 bits) where ROG2 stops
Table 38 Register PPG_ROG1_2_MSB (address: 0x72H) BIT PARAMETER 7 X 6 X X X X X X 5 4 3 2 1 0 2 MSBs of PPG_ROG2_STOP 2 MSBs of PPG_ROG2_START 2 MSBs of PPG_ROG1_STOP X 2 MSBs of PPG_ROG1_START
2001 May 04
36
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 39 Register VFC_CONTROL_0 (address: 0x73H) BIT PARAMETER 7 X X 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 6 5 4 3 2 1 0 RESET_VP_C: reset compression module of video processing RESET_VP_VF: reset video formatter of video processing
SAA8116
SCALE_DATA: limits the number of bits of the video formatter output 8 bits 7 bits 6 bits undefined PREFILTER_SEL_UV: select horizontal UV downscaling prefilter no prefilter (bypass) prefilter for downscaling to SIF with 3 taps prefilter for downscaling to QSIF with 5 taps undefined PREFILTER_SEL_Y: select horizontal Y downscaling prefilter no prefilter (bypass) prefilter for downscaling to SIF with 3 taps prefilter for downscaling to QSIF with 5 taps undefined
2001 May 04
37
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 40 Register VFC_CONTROL_1 (address: 0x74H) BIT PARAMETER 7 0 0 0 0 1 1 1 1 6 0 0 1 1 0 0 1 1 5 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 4 3 2 1 0
SAA8116
Q_TABLE_SELECT: select quantization table for the compression engine compression ratio = 2 (raw mode table) (by default) compression ratio = 3 compression ratio = 4 compression ratio = 5 compression ratio = 6; with one bit shift compression ratio = 7; with one bit shift compression ratio = 7.5; with one bit shift compression ratio = 8; with one bit shift LDC: length of DC coefficient used in the compression engine 6 bits 7 bits 8 bits undefined VOF: select video output format SIF compressed (by default) SIF uncompressed QSIF compressed QSIF uncompressed VGA compressed VGA raw compressed undefined undefined
2001 May 04
38
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 41 Register PIN_CONFIG_0 (address: 0x7EH) BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 0 reserved
SAA8116
P4_SEL: when enabled; pins are configured as general purpose outputs; otherwise they are connected to FV1; FV2 and FV3 0 1 0 1 disabled enabled (by default) ROG_SEL: select ROG signal according to CCD type PPG output ROG1 (Sony and Sharp CCD application) (by default) PPG output ROG2 (Panasonic CCD application)
Table 42 Register PIN_CONFIG_1 (address: 0x7FH) BIT PARAMETER 7 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 6 5 4 3 2 1 0 PR_DISABLE: control remote wake-up 2 enabled disabled (by default) SR_DISABLE: control remote wake-up 1 enabled disabled (by default) SPIF_SEL: select interface between sensor and preprocessor use serial interface (by default) use port P4[2 to 0] ASCLK_SEL: select ASCLK clock ASCLK = single pixel clock (by default) ASCLK = double pixel clock VSP_VH_SEL: select connection type of VSP pins V and H V = external V pulse (input); H = PPG_HD (output); VSP_VIN = PPG_VD V = external V pulse (input); H = VSP_HOUT (output); VSP_VIN = external V pulse V = PPG_VD (output); H = PPG_HD (output); VSP_VIN = PPG_VD V= VSP_VOUT (output); H = VSP_HOUT (output); VSP_VIN = 0 PCLK_INV: control pixel clock normal (by default) inverted VSP_CLK_SEL: select VSP clock VSP_CLK = CLK1 from PPG (by default) VSP_CLK = PCLK
2001 May 04
39
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Audio and power-management registers
SAA8116
A first MOVX@DPTR instruction enables to select the module (via DPH) and send the command. A second one communicates the data (read or write). Table 43 Register list ADDRESS Write registers 0 1 2 3 4 5 0x00H AUDIO_CLOCKS 0x01H RSTGEN 0x02H ANALOG_POWER 0x03H POWERMGT_N1 0x04H POWERMGT_N2 0x05H AUDIO audio clocks control reset generator control analog power control timer N1 (by default = 24) timer N2 (by default = 57) audio properties control see Table 44 see Table 45 see Table 46 byte byte see Table 47 NAME FUNCTION FORMAT
Read register 6 0x06H POWERMGT_STATUS power management status bits (read register) see Table 48
Table 44 Register AUDIO_CLOCKS (address: 0x00H) BIT PARAMETER 7 0 0 1 1 6 0 1 0 1 X 0 1 X 0 0 1 1 0 1 0 1 X 5 4 3 2 1 0 SET_DIVIDE: set clock dividers for ADC divide by 1 (by default) divide by 2 divide by 4 divide by 8 reserved DIS_CLK_AD: disable 48 MHz clock (ADC) enabled (by default) disabled reserved FCODE: set the PLL frequency 256 x 44.1 KHz (by default) 256 x 32 KHz 256 x 48 KHz 256 x 44.1 KHz reserved
2001 May 04
40
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 45 Register RSTGEN (address: 0x01H) BIT PARAMETER 7 0 1 X 0 1 X X X X X 6 5 4 3 2 1 0
SAA8116
UPC_RST_AUD26: reset generator for USB (aud26) module controlled by the power management (by default) forced reserved UPC_RST_ADIF: reset generator for audio module controlled by the power management (by default) forced reserved
Table 46 Register ANALOG_POWER (address: 0x02H) BIT PARAMETER 7 0 1 X 0 1 X 0 1 X X X 6 5 4 3 2 1 0 UPC_OSC_OFF: set power safe mode disabled (by default) enabled reserved UPC_PLL_OFF: control PLL power enabled (by default) disabled reserved UPC_ADL_OFF: control ADC power (left channel) enabled (by default) disabled reserved
2001 May 04
41
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 47 Register AUDIO (address: 0x05H) BIT PARAMETER 7 0 1 X 0 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 6 5 4 3 2 1 0 HP_EN: set high pass filter disabled enabled (by default) reserved MUTE_ON: set audio mute mute is off (by default) mute is on reserved gain control; 0 to 30 dB in steps of 2 dB 0 dB (by default) 2 dB .... 28 dB 30 dB
SAA8116
Table 48 Register POWERMGT_STATUS (address: 0x06H) BIT PARAMETER 7 X X X X X X X X 6 5 4 3 2 1 0 STATUS_POWERUPBIT: set to 1 after a Power-on reset (by default = 1) STATUS_BUSRESETBIT: set to 1 after a bus reset (by default = 0) STATUS_RESUMEBIT: set to 1 after a resume (by default = 0) STATUS_RW_BIT: set to 1 after remote wake-up is triggered (by default = 0) reserved
2001 May 04
42
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
USB registers
SAA8116
A first MOVX@DPTR instruction enables module selection (via DPH) and command transmission. A second MOVX communicates the data (read or write). Table 49 Register list ADDRESS Write registers 208 0xD0H SET_ADDRESS 216 0xD8H SET_EP_ENABLE 243 0xF3H GETSET_MODE Read registers 0 1 2 3 4 5 242 244 245 250 253 64 0x00H 0x01H 0x02H 0x03H 0x04H 0x05H 0xF2H 0xF4H 0xF5H 0xFAH 0xFDH SELECT_EP0_out SELECT_EP0_in SELECT_EP1_OUT SELECT_EP1_IN SELECT_EP2 SELECT_EP3 SET_BUFFER_FE GET_INTERRUPT GET_FRAMENUMBER VALIDATE_BUFFER GET_CHIPID select EP 0 out select EP 0 in select EP 1 out select EP 1 in select EP 2 select EP 3 clear selected EP buffer read interrupt register read current frame number validate selected EP read chip identifier see Table 53 see Table 53 see Table 53 see Table 53 see Table 53 see Table 53 byte see Table 54 note 1 byte note 2 byte byte byte byte byte byte byte byte note 3 byte set address set EP enable set mode see Table 50 see Table 51 see Table 52 NAME FUNCTION FORMAT
Read/write registers 0x40H SELECT_EP0_OUT_STATUS select EP; clear interrupt and get information of EP 0 (out) 65 0x41H SELECT_EP0_IN_STATUS select EP; clear interrupt and get information of EP 0 (in) 66 0x42H SELECT_EP1_OUT_STATUS select EP; clear interrupt and get information of EP 1 (out) 67 0x43H SELECT_EP1_IN_STATUS select EP; clear interrupt and get information of EP 1 (in) 68 0x44H SELECT_EP2_STATUS select EP; clear interrupt and get information of EP 2 69 0x45H SELECT_EP3_STATUS select EP; clear interrupt and get information of EP 3 70 0x46H SELECT_EP4_STATUS clear interrupt and get information of EP 4 71 0x47H SELECT_EP5_STATUS get information of EP 5 240 0xF0H RW_DATA read selected EP buffer 254 0xFEH GETSET_DEVICE_STATUS set device status Notes 1. The GET_FRAMENUMBER command returns the frame number of the last received Start Of Frame (SOF). The frame number is 11 bits wide; therefore two consecutive reads are needed to get the complete value. The first byte provides the LSBs; the second byte (bits 0 to 2) provides the 3 MSBs. Note: it is possible to read the first byte only. 2. The GET_CHIPID command is followed by two reads since the chip identification is 16 bits wide (see Tables 55 and 56). 3. The RW_DATA command can be followed by up to `n + 2' bytes read or write (n is the number of data bytes in the selected EP buffer). With read, it returns the contents of the selected EP data buffer. With write, it loads the data buffer of the selected EP.
2001 May 04
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Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 50 Register SET_ADDRESS (address: 0xD0H) Detailed description of the write (1 byte) following command 0xD0H BIT PARAMETER 7 X X X X X X X X 6 5 4 3 2 1 0 ENABLE_ADD: enable the function (by default = 0)
SAA8116
DEVICE_address: set the USB assigned address (by default = 0)
Table 51 Register SET_EP_ENABLE (address: 0xD8H) Detailed description of the write (1 byte) following command 0xD8H BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 10 0 reserved ENABLE_EP: enable end-point Non-control end-points are disabled (by default) Non-control end-points are enabled
Table 52 Register GETSET_MODE (address: 0xF3H) Detailed description of the write (one byte) following command 0xF3H; notes 1, 2 and 3 BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 0 1 0 1 0 1 Notes 1. GETSET_MODE command can write from 1 to 4 consecutive bytes. The detailed description above concerns byte 0. 2. GETSET_MODE bytes 1 and 2 are used to set the size of the isochronous video packets. Byte 1 corresponds to the LSB to define the packet size. Bits 0 and 1 of byte 2 set the 2 MSBs. By default, the two bytes are forced to 0. 3. GETSET_MODE byte 3 sets the FIFO offset. 2 1 0 reserved FIFO_ACTIVE: set the video FIFO status FIFO is inactive; only zero-length packet are sent upstream functional mode (by default) ALWAYS_PLLCLOCK: control internal clock signals clocks and PLL are stopped whenever not needed (e.g. suspend mode) clocks and PLL are always running even in suspend mode (by default) INTERRUPT_ONNAK: control transaction reporting only successful transactions are reported NAK is reported and generates an interrupt (by default)
2001 May 04
44
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 53 Register SELECT_EP0_OUT (address: 0x00H) Detailed description of the optional read (1 byte) following command 0x00H; note 1 BIT PARAMETER 7 X 6 X 5 X 0 1 0 1 0 1 0 1 4 3 2 1 0 reserved SENT_NAK: a NAK is not sent (by default) a NAK is sent by the device PACKET_OVERWRITTEN: not overwritten (by default)
SAA8116
the previously received packet was overwritten by a setup packet SETUP_PACKET: give the status of the last received packet not a setup packet (by default) last received packet for the selected EP was a setup packet STALL_PACKET: give the status of the selected EP not stall (by default) stall BUFFER_STATUS: give the EP buffer status; note 2; this bit is cleared by executing the SET_BUFFER_FE command 0 1 buffer not full (by default) buffer of the selected EP is full
Notes 1. The SELECT_EPX_XX command selects the corresponding EP buffer. It can be followed optionally by a data read, which provides the EP status to the microcontroller (see the detailed description above). Whatever the EP (from 0 to 3) or its direction, the sequence is the same. Note that isochronous EP cannot be selected in this way. 2. BUFFER_STATUS: in case of an IN endpoint; this bit is set by the VALIDATE_BUFFER command. Table 54 Register GET_INTERRUPT (address: 0xF4H) Detailed description of the read (1 byte) following command 0xF4H BIT PARAMETER 7 X X X X X X X X 6 5 4 3 2 1 0 DEVICE_EVENT: an event occurred in the device PHYSICAL_EP6: interrupt signal comes from (logic) EP4 PHYSICAL_EP5: interrupt signal comes from (logic) EP3 PHYSICAL_EP4: interrupt signal comes from (logic) EP2 PHYSICAL_EP3: interrupt signal comes from (logic) EP1 in PHYSICAL_EP2: interrupt signal comes from (logic) EP1 out PHYSICAL_EP1: interrupt signal comes from (logic) EP0 in PHYSICAL_EP0: interrupt signal comes from (logic) EP0 out
2001 May 04
45
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Table 55 Register GET_CHIP_ID BYTE 0 (address: 0xFDH) Detailed description of the read (byte 0) following command 0xFDH BIT PARAMETER 7 X 6 X 5 X 4 X 3 X X X X 2 1 0
SAA8116
PRODUCT_ID: 5 LSBs of the product identification (by default = 10011) REVISION_NB: revision number (by default = 001)
Table 56 Register GET_CHIP_ID BYTE 1 (address: 0xFDH) Detailed description of the read (byte 1) following command 0xFDH BIT PARAMETER 7 X 6 X 5 X 4 X 3 X 2 X X X 1 0 CUSTOMER_ID: customer identification (by default = 110011) PRODUCT_ID: 2 MSBs of the product identification (by default = 00)
2001 May 04
46
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); note 1. SYMBOL VDD Vn supply voltage voltage on pins GND and AGND all other pins Tstg Tamb Tj Note 1. Stress beyond these levels may cause permanent damage to the device. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 53 storage temperature ambient temperature junction temperature -0.5 -0.5 -55 0 -40 +4.0 PARAMETER MIN. -0.5 MAX. +4.0
SAA8116
UNIT V V V C C C
VDD + 0.5 +150 70 +125
UNIT K/W
2001 May 04
47
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
CHARACTERISTICS VDD = VDDD = VDDA = 3.3 V 10%; Tamb = 0 to 70 C; unless otherwise specified; note 1. SYMBOL Supplies VDD VDDD VDDA IDDD(tot) IDDA(tot) IDDQ(susp) VIL VIH VOL VOH Vref VO IO IDDA Vref VO IO supply voltage supply voltage for digital core analog supply voltage total digital supply current total analog supply current total suspend current VDD = VDDD = 3.3 V; Tamb = 25 C 3.0 3.0 3.0 - 3.3 3.3 3.3 65(2) 16 - - - - - 1.50 3.0 5 PARAMETER CONDITIONS MIN. TYP.
SAA8116
MAX.
UNIT
3.6 3.6 3.6 85(3) - 400(3)
V V V mA mA A V V
VDDA = 3.3 V; Tamb = 25 C - VDDA = 3.3 V; Tamb = 25 C - - 2
Digital data and control inputs LOW-level input voltage HIGH-level input voltage 0.8 - 0.1VDD VDD - - 10
Digital data and control outputs LOW-level output voltage HIGH-level output voltage 0 0.9VDD at 0.5VDDA VDDA = 3.0 V - - - - at 0.5VDDA VDDA = 3.0 V - - - V V
LDO supply filter reference voltage output voltage on pin LDOUT output current on pin LDOUT V V mA
Microphone supply supply current reference voltage output voltage on pin MICSUPPLY output current on pin MICSUPPLY 0.85 1.50 2.7 - 1.2 - - 2.0 mA V V mA
Audio low noise amplifier TRANSFER FUNCTION Ri IDDA A THD Vo(rms) VOO BIASING Iref reference current - 10 - A input resistance supply current amplification total harmonic distortion output voltage (RMS value) output offset voltage note 4 3.5 - 29 - - - 5.0 0.85 30 -77 - 0.0 - 1.2 31 -70 800 1.0 k mA dB dB mV mV
2001 May 04
48
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA8116
MAX.
UNIT
Programmable audio gain amplifier TRANSFER FUNCTION Ri IDDA VOO A THD BIASING Iref fi(clk) fo(clk) reference current - - note 5 - - - B bandwidth damping coefficient - - 10 - - - - - - - A MHz MHz MHz MHz kHz input resistance supply current output offset voltage amplification total harmonic distortion A = 0 dB; note 4 A = 30 dB; note 4 A = 0 dB A = 30 dB 7.0 - - - 0.2 - - 10.5 0.45 1.0 14 - -89 -66 25 0.6 2.0 30 32 -85 -62 k mA mV mV dB dB dB
Audio phase-locked loop clock input frequency clock output frequency 48 8.1920 11.290 12.288 2.3 0.98
Audio ADC ( converter) INPUTS fi Vi(rms) N Nbit Nbit(eq) DRi fclk THD input signal frequency input voltage (RMS value) order of the number of output bits equivalent output resolution (bit) dynamic range at input clock frequency clock frequency duty factor total harmonic distortion note 6 1 - - - - - - - - - 800 20 - - - - - 5.6448 - -60 dB MHz % dB kHz mV
TRANSFER FUNCTION 3 1 16 96.6 - 50 -73
ATX transceiver full speed mode: pins ATXDP and ATXDN DRIVER CHARACTERISTICS tt(rise) tt(fall) tt(match) Vcr Zo rise transition time fall transition time transition time matching output signal crossover voltage driver output impedance steady state drive CL = 50 pF CL = 50 pF note 7 4 4 90 1.3 30 - - - - - 20 20 110 2.0 42 ns ns % V
2001 May 04
49
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SYMBOL PARAMETER CONDITIONS - - MIN. TYP. - -
SAA8116
MAX.
UNIT
RECEIVER CHARACTERISTICS fi(D) tframe Notes 1. Including the current through the external 1.5 k resistor connected to ATXDP. 2. Typical: VGA at 15 fps. 3. Maximum: SIF at 30 fps. 4. The distortion is measured at HIGH level; 1 kHz and Vo = 800 mV (RMS). 5. Frequencies depend on PLL settings; see also Table 6. input voltage 6. Defined here as: 20 x log -----------------------------------------------------------------------------equivalent input noise voltage t t ( rise ) 7. Transition time matching: t t ( match ) = ------------- x 100% t f ( fall ) data input frequency rate frame interval 12.00 1.000 Mbits/s ms
2001 May 04
50
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
TIMING VDDD = VDDA = 3.3 V 10%; Tamb = 0 to 70 C. SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA8116
MAX.
UNIT
Data input related to ASCLK for CCD sensors; (see Fig.10) PINS PXL0 TO PXL7 tsu(i)(D) th(i)(D) td1 td2 td3 td4 td5 td6 td7 tWH(FH1) tWL(FH2) tWL(FCDS) tWL(FS) tWL(RG) tr data input set-up time data input hold time 1.5 1.5 -4 0 10.5 10 0 -3 2 38 41 6 18 20 40 note 1 - - - - - note 1 - - - - - 4 4 4 4 4 - - - - - ns ns ns ns ns 4 4 4 4 4 - - - - - ns ns ns ns ns - - -2 1.5 12 12.5 2 -1.5 6 39.5 42.5 7 20.5 21.5 43.5 - - 0 3 13.5 15 4 0 10 - - - - - - ns ns
PPG high-speed pulses for SONY ICX098AK VGA CCD sensor at 30 fps; (see Fig.11) delay between falling edge FH2 and rising edge FH1 delay between rising edge FH2 and falling edge FH1 delay between falling edge FH1 and rising edge FCDS delay between rising edge FH1 and rising edge FS delay between rising edge FH1 and falling edge RG delay between falling edge ASCLK and rising edge FH1 delay between rising edge ASCLK and falling edge FH1 FH1 pulse width HIGH FH2 pulse width LOW FCDS pulse width LOW FS pulse width LOW RG pulse width LOW rise time pulse FH1 pulse FH2 pulse RG pulse FCDS pulse FS tf fall time pulse FH1 pulse FH2 pulse RG pulse FCDS pulse FS Note 1. CL = 11 pF; Tamb = 25 C. ns ns ns ns ns ns ns ns ns ns ns ns ns
tWL(ASCLK) ASCLK pulse width LOW
2001 May 04
51
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SAA8116
handbook, full pagewidth
ASCLK tsu(i)D
th(i)D
PXL[9:0]
FCE746
Fig.10 Data input timing.
handbook, full pagewidth
tWH(FH1) 50% td1 td2 50% tWL(FH2) 50% 50%
FH1
FH2 50%
FCDS
50%
50% td3 tWL(FCDS) tWL(FS) 50% 50% td4
FS tWL(RG) td5 RG 50% td6 ASCLK 50% tWL(ASCLK) 50% td7 50%
FCE745
Fig.11 PPG high-speed pulses for Sony ICX098AK VGA CCD sensor.
2001 May 04
52
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
APPLICATION INFORMATION
SAA8116
In the event that the internal ROM is used (pin EA set HIGH), it is strongly recommended to connect pins P0.0 to P0.7 to ground to avoid any leakage that would increase the current in suspend mode.
handbook, full pagewidth
EPROM (optional) AD14 to AD8
EEPROM
P0.7 to P0.0
12 MHz PSEN XOUT ALE SDA SCL XIN
PCLK ASCLK PXL9 to PXL0 CCD SENSOR
EA
TDA8787A SDATA
SCLK STROBE
SAA8116
DELAYATT
XSEL LED SNAPRES PRIVRES PORE PSEL
REF1 LNAOUT
MICSUPPLY
LDOOUT
PGAININ
MICIN
LDOFIL
FULLPOWER
V-DRIVER
FS, FCDS, DCP, BCP
LDOIN
Vref2
Vref3
ATXDP ATXDN 5VBUS LDO
USB
FH1, FH2, RG, ROG
LDO FV1, FV2, FV3, FV4, CRST SMP 3.3 V 3.3 V
FCE675
Fig.12 CCD sensor application.
2001 May 04
53
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SAA8116
handbook, full pagewidth
EPROM (optional) AD14 to AD8 P0.7 to P0.0
EEPROM
PSEN
SDA
SCL
ALE
EA
12 MHz XOUT XIN
CMOS SENSOR
V ASCLK PCLK PXL7 to PXL0
SAA8116
DELAYATT
XSEL LED SNAPRES PRIVRES PORE PSEL
REF1 LNAOUT
PGAININ
MICSUPPLY
LDOOUT
MICIN
LDOFIL
FULLPOWER
LDOIN
Vref2
Vref3
ATXDP ATXDN 5VBUS LDO
USB
LDO
3.3 V
3.3 V
FCE676
Fig.13 CMOS sensor application.
2001 May 04
54
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
PACKAGE OUTLINES LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SAA8116
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 00-01-19 00-02-01
2001 May 04
55
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SAA8116
TFBGA112: plastic thin fine-pitch ball grid array package; 112 balls; body 7 x 7 x 0.8 mm
SOT630-1
D
B
A
ball A1 index area
A E
A2 A1 detail X
A e1 e b
w M
vMB vA vMA y
M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 X 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.12 A1 0.28 0.16 A2 0.84 0.76 b 0.37 0.27 D 7.1 6.9 E 7.1 6.9 e 0.5 e1 5.5 v 0.1 w 0.15 y 0.12 y1 0.1 5 mm e1 e
OUTLINE VERSION SOT630-1
REFERENCES IEC JEDEC MO-195 EIAJ
EUROPEAN PROJECTION
ISSUE DATE 00-07-20
2001 May 04
56
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
SAA8116
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2001 May 04
57
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
Suitability of surface mount IC packages for wave and reflow soldering methods
SAA8116
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2001 May 04
58
Philips Semiconductors
Product specification
Digital PC-camera signal processor including microcontroller and USB interface
DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. PURCHASE OF PHILIPS I2C COMPONENTS DISCLAIMERS
SAA8116
Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2001 May 04
59
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2001
Internet: http://www.semiconductors.philips.com
SCA 72
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/03/pp60
Date of release: 2001
May 04
Document order number:
9397 750 08198

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